The attention of the global semiconductor academic and industrial community was focused on this morning’s IEEE International Symposium on Circuits and Systems (ISCAS 2026). Huawei Semiconductor’s Chief Technology Officer delivered a keynote presentation titled “Exploring Future Design Methodologies for Electronic Systems” and publicly introduced for the first time a systematic technological theory internally known as “Logic Folding.” The theory reveals that in the post-Moore’s Law era, breakthrough improvements in effective transistor density and system-level performance can be achieved through multidimensional folding and restructuring at the logic level. This discovery provides an entirely new theoretical foundation for achieving major chip performance gains even under limitations in advanced semiconductor manufacturing processes.

According to the official conference agenda summary, Huawei HiSilicon’s research team identified and summarized new evolutionary rules driving the future development of semiconductor device systems through extensive research into next-generation electronic system architectures. The discovery — already being referred to externally as “Huawei’s New Law” — centers around Logic Folding technology. Its core concept is no longer to rely solely on improving lithography precision in order to increase transistor density, but instead to achieve breakthroughs in effective transistor density and performance through multidimensional folding and restructuring at the system logic level.

Compared with traditional manufacturing process advancements, the disruptive nature of this technology lies in its creation of an entirely new paradigm that goes beyond pure process miniaturization. More specifically, the Logic Folding principle uses innovative logic gate circuit design to integrate operations that previously required multiple transistors executing sequentially into a single complex unit capable of processing multidimensional logic states in parallel. This allows information density and computational efficiency to break free from strict dependence on physical transistor scaling, achieving what Huawei describes as “equivalent high-density” performance.

For example, Huawei’s breakthroughs in ternary logic gate circuit technology provide foundational support for Logic Folding. By introducing three logic states — “-1, 0, and 1” — the number of single-variable function types expands from 16 in traditional binary systems to 27. Under equivalent computing power conditions, this approach can reportedly reduce transistor requirements by approximately 30% to 40% while lowering power consumption to roughly one-third of traditional architectures. This reconstruction of foundational mathematical logic enables chips to achieve major increases in effective transistor density at the macro system level.

The reason this new technology can deliver such dramatic system-level performance improvements lies in its fundamentally disruptive redesign of chip operational workflows. Logic Folding is not simply about making individual transistors “smarter.” Instead, it introduces comprehensive optimization through a complete redesign of system architecture. In chips designed using Logic Folding principles, data-processing pipelines can be dramatically simplified. Traditional stages such as instruction fetching, decoding, and execution can potentially be merged into a single “Logic Folding unit” capable of completing the entire process simultaneously. In certain AI inference tasks requiring extremely low latency, this approach may reportedly improve processing speed by as much as 47%.

From an industry perspective, this theory provides a critical new foundation and reference framework for semiconductor development in the post-Moore era. Its potential impact spans SoC design, semiconductor manufacturing processes, and the broader technological evolution path of the semiconductor industry over the next decade. According to industry participants attending the conference, Huawei’s “Logic Folding” framework may fundamentally reshape how computing power is deployed, making chip architectures more flexible and intelligent. Competitive focus within the semiconductor industry may gradually shift away from pure process-node competition toward integrated innovation combining “architecture + algorithms.”

Of course, Logic Folding technology still faces substantial challenges during its early stages of practical implementation. For example, more complex logic states impose significantly stricter requirements on noise tolerance, thermal stability, and supporting EDA software ecosystems. These surrounding toolchains and ecosystems will also require substantial upgrades. Nevertheless, as Huawei and other leading companies continue advancing engineering implementation and open-source ecosystem development, Logic Folding undoubtedly opens an entirely new and highly imaginative path for chip development in the post-Moore’s Law era.